Increasingly large portions of electronic systems are being implemented in software and its development cost starts dominating the cost for the whole system. Software is also becoming the critical part of the development schedule, mainly because deploying and testing it on the real target hardware is complicated.
Our activities in the ESA-supported "HW-SW SystemC Co-Simulation SoC Validation Platform" project aim at the implementation and validation of an efficient methodology allowing software to be developed before the final hardware is ready. We are therefore developing a design flow for the implementation of virtual platforms (VP) based on Transaction Level Models (TLMs) in SystemC.
A TLM can be used to describe the timing and functionality of a system component and its communication interface at a high abstraction level. Embedded in a virtual platform these models are sufficiently accurate to allow early software development and verification in a realistic environment as well as the functional verification of the modelled hardware. Thus, the capability of early design space exploration completes our design flow to be applicable for full hardware / software co-design.
The convenience of the overall approach will be demonstrated by implementing a proof-of-concept virtual platform (VP) in different configurations, one of which is depicted in Figure 1. In additional configurations Multi-Processor System-on-Chip (MPSoC) platforms will be implemented containing four and more LEON 2 or LEON 3 cores.
The tasks involved comprise
The development and application of methods for the generation and verification of TLMs for the existing IP components,
- The choice of a suitable virtual platform infrastructure,
- The development, verification, and application of a design flow for VP implementation,
- The development of a simulation environment enabling the verification of the VPs, and
- The documentation of all applied and developed methods and flows.
The key contribution of the project will be a fully validated Electronic System Level Design (ESL) flow. This will enable efficient HW / SW co-design of complex SoC platforms based on Transaction Level Models and virtual platforms.
