Eberhard Zehendner

Prof. Dr.
Room: 3231
Work+49 3641 946385
c3e
Institut für Informatik
Friedrich-Schiller-Universität Jena
Work
Ernst-Abbe-Platz 2
D-07743 Jena
Germany

Sprechstunde: Dienstags, 14.00 - 15.00 Uhr

Lectures


Aktuell: Vorlesung "Automatisches Parallelisieren" [Materialien]

Aktuell: Vorlesung "IT-Sicherheit" [Materialien]

Aktuell: Seminar "Low Power Computer Arithmetic" [Materialien]

Aktuell: Seminar "Informatik und Gesellschaft (Thema: WikiLeaks)" [Materialien]


Vorlesung "Phänomene der Rechnerarithmetik"

Vorlesung "Grundlagen der Rechnerarithmetik" [Materialien]

Seminar "Rechnerarithmetik in modernen Mikroprozessoren"

Seminar "Ausgewählte Aspekte der Rechnerarithmetik"

Seminar "Informatik und Gesellschaft (Thema: Gefahr im Internet – Gefahr aus dem Internet)" [Materialien]


Vorlesung "Automatisches Parallelisieren" [Materialien]

Seminar "New Frontiers in Computer Arithmetics" [Materialien]

Seminar "Informatik und Gesellschaft (Thema: Datenschutz und Datenpannen)" [Materialien]


Seminar "Gleitkomma-Arithmetik" [Materialien]

Seminar "Low Power Hardware Design"

Proseminar "Informatik und Gesellschaft (Thema: Alltag Überwachung)" [Materialien]


Vorlesung "Rechnerarithmetik" [Materialien]

Seminar "Gleitkomma-Addition in CMOS"

Seminar "Low Power Computer Arithmetics" [Materialien]

Proseminar "Informatik und Gesellschaft (Thema: Totale Überwachung)" [Materialien]

Archived lectures

Projects

ENEFCA

Energie-Efficient Computer Arithmetic

The main goal of ENEFCA is to investigate properties of computer arithmetic components based on redundant number representation. We focus on RTL-design und gate-level-analysis of energy-efficient carry-save and signed-digit arithmetic used for adder, multiplier, multiply-accumulate and digital filter design.

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ERA

Error Resilient Arithmetic

The main goal of ERA is to investigate error resilience detection and correction capabilities of differnet redundant number representations. We focus on RTL-design und gate-level-analysis of detection and correction methodologies used for adder, multiplier, multiply-accumulate and digital filter design.

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Publications

  • D. Neuhäuser, E. Zehendner : VHDL Code Generator for Optimized Carry-Save Reduction Strategy in Low Power Computer Arithmetic in Proceedings of the 2nd European Conference of Circuits Technology and Devices, WSEAS Press 2011, ISBN: 978-1-61804-056-5, 229 - 235 more ...
  • D. Neuhäuser, E. Zehendner : On Carry-Save Strategies for Multiply-Accumulate Arithmetic in Proceedings of the 2nd European Conference of Computer Science, WSEAS Press 2011, ISBN: 978-1-61804-056-5, p. 235 - 240 more ...
  • D. Neuhäuser, E. Zehendner : Resilient data encoding for fault-prone signal transmission in parallelized signed-digit based arithmetic in Proceedings of the 10th Workshop on Parallel Systems and Algorithms, ARCS 2012 (accepted) more ...

more puplications